1. Field of the Invention
The present invention relates to an embedded memory device, and more particularly, to a data input/output (I/O) circuit of an embedded memory device.
2. Description of the Related Art
With the recent demand for an increase in speed of dynamic random access memories (DRAMs), DRAMs are merged into logic circuits, and embedded DRAMs having a wide bandwidth have come into general use. Such embedded DRAMs are previously implemented in the form of a unit macro, so that they can support various storage densities and I/O data widths as desired by users. Also, the embedded DRAMs are designed using compiler techniques to shorten the time required for designing. For example, by using compiler techniques, embedded DRAMs having various I/O data widths such as X4, X16, . . . , X128, and X256 can be designed.
FIG. 1 illustrates a data I/O circuit 1 of a conventional embedded DRAM.
Referring to FIG. 1, sub memory cell blocks MC0 through MC127 that share word lines WL are spaced apart by a predetermined distance. Also, bit line sense amplifying unit groups BG0 through BG127 and I/O lines IO0, IO0B through IO127, IO127B are arranged adjacent to the sub memory cell blocks MC0 through MC127.
In FIG. 1, since the configurations of the sub memory cell blocks MC0 through MC127 are substantially identical, only the sub memory cell blocks MC0 and MC1 are illustrated in detail. Also, since the configurations of the bit line sense amplifying unit groups BG0 through BG127 are substantially identical, only the bit line sense amplifying unit groups BG0 and BG1 are illustrated in detail.
Each of the bit line sense amplifying unit groups BG0 through BG127 includes a plurality of bit line sense amplifying units BS1 through BS8. In FIG. 1, the plurality of bit line sense amplifying units BS1 through BS8 are connected between bit lines BLs and BLBs of the sub memory cell blocks MC0 through MC127 and the I/O lines IO0, IO0B through IO127, IO127B. Data I/O units U1 through U64 are connected to the I/O lines IO0, IO0B through IO127, IO127B, respectively.
The data I/O circuit 1 of a general embedded DRAM, configured as described above, can support various I/O data widths such as X4, X16, . . . , X128 through I/O muxing.
Next, a data I/O circuit of embedded DRAM according to conventional art will be described with reference to FIGS. 2 and 3. FIG. 2 illustrates in detail a portion of the data I/O circuit of embedded DRAM according to conventional art, and FIG. 3 is a timing diagram for signals associated with the data I/O circuit of FIG. 2.
Referring to FIG. 2, in the data I/O circuit of embedded DRAM according to conventional art where I/O lines are 2:1 muxed, two bit line sense amplifying units 10 and 20 and a data I/O unit 30 corresponding thereto are only illustrated.
The bit line sense amplifying units 10 and 20 are respectively connected to bit lines BL0 and BL0B and bit lines BL1 and BL1B of different sub memory cell blocks (MC0 and MC1 of FIG. 1) and share a column selection line (not shown).
The bit line sense amplifying unit 10 includes bit line precharge circuits 11a and 11b, sense amplifying circuits 12a and 12b, and gate circuits 13a and 13b, which are connected to the bit lines BL0 and BL0B. The gate circuits 13a and 13b are also connected to I/O lines IO0 and IO0B.
The bit line sense amplifying unit 20 includes bit line precharge circuit 21a and 21b, sense amplifying circuits 22a and 22b, and gate circuits 23a and 23b, which are connected to the bit lines BL1 and BL1B. The gate circuits 23a and 23b are also connected to I/O lines IO1 and IO1B.
The data I/O unit 30 is connected to an input buffer 40 and an output buffer 50. The data I/O unit 30 includes I/O precharge circuits 31 and 32 and I/O sense amplifier and drivers 33 and 34.
Here, for high-speed data read and write operations, the bit line sense amplifying units 10 and 20 include the gate circuits 13a and 23a that are enabled during a read operation and the gate circuits 13b and 23b that are enabled during a write operation. Also, for a high-speed read operation, the gate circuit 13a generates a current corresponding to a voltage difference between the bit lines BL0 and BL0B and the gate circuit 23a generates a current corresponding to a voltage difference between the bit lines BL1 and BL1B.
For example, when the I/O lines IO0 and IO0B are selected during a read operation, the gate circuit 13a is turned on in response to a column selection signal RCSL. Then, the gate circuit 13a generates the current corresponding to the voltage difference between the bit lines BL0 and BL0B. The current generated by the gate circuit 13a flows into the I/O lines IO0 and IO0B.
At this time, since the gate circuit 23a shares the column selection line (not shown) with the gate circuit 13a, it is also turned on in response to the column selection signal RCSL.
Here, a sub memory cell block (MC0 of FIG. 1) including the bit lines BL0 and BL0B and a sub memory cell block (MC1 of FIG. 1) including the bit lines BL1 and BL1B share word lines (WL of FIG. 1).
Since the word lines are being enabled when the I/O lines IO0 and IO0B are selected, after the gate circuit 23a is turned on, the current, generated by the gate circuit 23a, flows from the bit lines BL1 and BL1B into the I/O lines IO1 and IO1B. As a result, although the I/O lines IO1 and IO1B are not selected, a voltage difference occurs between the I/O lines IO1 and IO1B, as shown in FIG. 3.
Similarly, when the I/O lines IO0 and IO0B are selected during a write operation, the gate circuits 13b and 23b are turned on in response to a column selection signal WCSL.
As a result, although the I/O lines IO1 and IO1B are not selected, the current, generated by the gate circuit 23b, flows from the bit lines BL1 and BL1B into the I/O lines IO1 and IO1B. Thus, as shown in FIG. 3, a voltage difference occurs between the I/O lines IO1 and IO1B.
As described above, in the data I/O circuit of embedded DRAM according to conventional art, during the read or write operation, current flows through I/O lines that are not selected, resulting in high power consumption. In particular, power consumption becomes a serious concern when the I/O data width is set to be narrow. For example, in embedded DRAM capable of supporting a maximum I/O data width of X128, when I/O lines are 16:1 muxed and the embedded DRAM are then set to I/O data width X8, the number of I/O lines that are not selected during the read or write operation is much greater than that of I/O lines that are selected during the read or write operation. Thus, power consumption is unnecessarily increased.